A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation

スポンサーリンク

概要

• 論文の詳細を見る

• This paper proposes a behavioral synthesis system for asynchronous circuits with bundled-data implementation. The proposed system is based on a behavioral synthesis method for synchronous circuits and extended on operation scheduling and control synthesis for bundled-data implementation. The proposed system synthesizes an RTL model and a simulation model from a behavioral description specified by a restricted C language, a resource library, and a set of design constraints. This paper shows the effectiveness of the proposed system in terms of area and latency through comparisons among bundled-data implementations synthesized by the proposed system, synchronous counterparts, and bundled-data implementations synthesized by using a behavioral synthesis method for synchronous circuits directly.

• 一般社団法人情報処理学会の論文
• 2009-02-17

著者

• Chris Myers

  The University of Utah, USA

• Tomohiro Yoneda

  National Institute of Informatics, Japan

• Naohiro Hamada

  The University of Aizu, Japan

• Yuki Shiga

  The University of Aizu, Japan

• Takao Konishi

  The University of Aizu, Japan

• Hiroshi Saito

  The University of Aizu, Japan

• Takashi Nanya

  The University of Tokyo, Japan

関連論文

• A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation

スポンサーリンク