AHigh-Performance Multiplierless Hardware Architecture of the Transform Applied to H.265/HEVC Emerging Video Coding Standard

概要

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This paper presents a hardware architecture of the transform applied in the emerging video coding standard HEVC (High Efficiency Video Coding). The transform coding tool is one of the innovational feature adopted by HEVC, because of the variable transform matrix size (from 4x4 to 32x32), while the traditional transform size is 4x4 and 8x8 used by the H.264/AVC. The hardware design proposed in this paper focuses on low cost and high throughput. To obtain such objectives, some simplification strategies were adopted during the implementation, such as reusing part of larger size transform structure by smaller size, and turning multiplications by constant into shift and sum operations. Moreover, the transform architecture proposed in this paper was implemented in the form of pipeline structure. The designed architecture was described us ing Verilog HDL, and synthesis on an Altera Cyclone IV E FPGA. The results showed that the design achieved a maximum operation frequency of 114.29 MHz, and can process 190.50Msamples/s on average, allowing it to process Class A video sequences (2560x1600 pixels, 30fps) and Full HD sequences (1920x1080 pixels, 60fps). Therefore, the proposed architecture is capable to processing video sequences with high definition in real time. To the best of our knowledge, this is the first work in the literature that presents fully hardware results on FPGA platform for the HEVC transforms with a variable size from 4x4 to 32x32.
2012-09-13