Analysis of SER Improvement by Soft Error Tolerant Latches

概要

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In this paper we investigate SER improvement of various soft error tolerant latches. Many soft error tolerant circuit designs have been proposed not only for DRAM, SARM but also for latches and flip-flops. However relative comparison of different designs has not been fully investigated so for. We propose a simulation based SER analysis method which can be applied to these circuits so that relative comparison of SER improvement can be accurately analyzed. For the experiments, we use three different soft error tolerant latches namely DICE, BISER, and TMR; then SER of each circuit is fully investigated. The DICE latch increases soft error resilience by adopting local redundancy enabling feedback from cross coupled nodes, on the other hand BISER and TMR latches archive soft error resilience by duplicating vulnerable normal D-latches with some logic gates to filter erroneous outputs. From our simulation results, it is confirmed that DICE circuit outperforms other circuits with minimum area, delay and energy consumption.
2012-07-25