A Preliminary Study on the Design of Hierarchical Memory Management for Heterogeneous Architectures

概要

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Heterogeneous architectures, where a multicore processor, which is optimized for fast single-thread performance, is accompanied with a large number of simpler, but more power-efficient cores optimized for parallel workloads, are receiving a lot attention recently. Currently, these co-processors, such as Intel's Many Integrated Core (MIC) software development platform, come with a limited on-board RAM, which requires partitioning computational problems manually into pieces that can fit into the device's memory, and at the same time, efficiently overlapping computation and communication. In this paper we explore the design considerations for operating system (OS) assisted hierarchical memory management, relying on the capabilities of the Intel MIC's memory management unit (MMU). We are aiming at transparent data movement between the device and the host memory, as well as tight integration with other OS services, such as file and network I/O.
2012-07-25