Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation
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概要
- 論文の詳細を見る
This paper proposes an instruction pre-execution scheme for a high performance processor that reduces latency and early scheduling of loads. Our scheme exploits the difference between the amount of instruction-level parallelism available with an unlimited number of physical registers and that available with an actual number of physical registers. We introduce the two-step physical register deallocation scheme which deallocates physical registers at the renaming stage as a first step and eliminates pipeline stalls caused by a shortage of physical registers. Instructions wait for the final deallocation as a second step in the instruction window. While waiting the scheme allows pre-execution of instructions that enables prefetching of load data and early calculation of memory effective addresses. Our evaluation results show that our scheme improves the performance significantly and achieves a 1.26 times speedup over a processor without a prefetcher. If combined with a stride prefetcher it achieves a 1.18 times speedup over a processor with a stride prefetcher.
- 一般社団法人情報処理学会の論文
- 2008-08-21
著者
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Hideki Ando
Department Of Computational Science And Engineering Nagoya University
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Yusuke Tanaka
Department Of Computational Science And Engineering Nagoya University
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Toshio Shimada
Department Of Electrical Engineering And Computer Science Nagoya University
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Akihiro Yamamoto
Department of Electrical Engineering and Computer Science Nagoya University Presently with Renesas T
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Akihiro Yamamoto
Department Of Electrical Engineering And Computer Science Nagoya University Presently With Renesas T