A-30 Property Verification for Arithmetic Logical Circuit by using Proof Checker
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概要
- 論文の詳細を見る
- FIT(電子情報通信学会・情報処理学会)推進委員会の論文
- 2002-09-13
著者
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WASAKI Katsumi
Faculty of Engineering, Shinshu University
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Wasaki Katsumi
Faculty Of Engineering Shinshu University
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Bancerek Grzegorz
Institute of Computer Science, University of Bialystok
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Bancerek Grzegorz
Institute Of Computer Science University Of Bialystok
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Yamaguchi Shin'nosuke
Faculty Of Engineering Shinshu University
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- A-30 Property Verification for Arithmetic Logical Circuit by using Proof Checker