Modeling and Simulation of ΔΣ Fractional-N PLL Frequency Synthesizer in Verilog-AMS(Nonlinear Circuits,<Special Section>Nonlinear Theory and its Applications)
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概要
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A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the ΔΣ modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the ΔΣ modulator. The spur-minimizing effect of an odd initial condition on the first accumulator of the ΔΣ modulator is verified. Sequence length control and its effect on the fractional-N frequency synthesizer are also discussed. The simulated results are in agreement with prior published data on fractional-N synthesizers and with new measurement results.
- 社団法人電子情報通信学会の論文
- 2007-10-01
著者
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Kennedy Michael
Department Of Microelectronic Engineering And Tyndall National Institute University College Cork
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YE Zhipeng
Department of Microelectronic Engineering and Tyndall National Institute, University College Cork
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CHEN Wenbin
Department of Microelectronic Engineering and Tyndall National Institute, University College Cork
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Ye Zhipeng
Department Of Microelectronic Engineering And Tyndall National Institute University College Cork
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Chen Wenbin
Department Of Microelectronic Engineering And Tyndall National Institute University College Cork
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KENNEDY Michael
Department of Electronic and Electrical Engineering, University College Dublin
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Kennedy Michael
Department of Electrical and Electronic Engineering, University College Cork
関連論文
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