V_<dd> Gate Biasing RF CMOS Amplifier Design Technique Based on the Effect of Carrier Velocity Saturation(Active Devices/Circuits,<Special Section>Microwave and Millimeter-Wave Technology)

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概要

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• One of the interesting submicron MOS FET characteristics is the effect of carrier velocity saturation (CVS) on the drain current. In the CVS region, the transconductance becomes constant independent both of the gate and the drain voltage. In this paper, RF MOS amplifier design technique using the CVS region has been proposed. By setting the FET gate bias to the power supply voltage V_<dd>, stable operation against V_<dd> variations can be achieved with a simple circuit configuration. By using this, a 5GHz amplifier has been designed and fabricated by using 0.18-μm CMOS process technology. The chip has been operated with a gain variation less than 1dB having a peak gain of 13.5dB from 1.2 to 2.9V V_<dd>

• 一般社団法人電子情報通信学会の論文
• 2007-09-01

著者

• Ishihara Noboru

  Electronics And Computing Graduate School Of Engineering Gunma University

関連論文

• V_ Gate Biasing RF CMOS Amplifier Design Technique Based on the Effect of Carrier Velocity Saturation(Active Devices/Circuits,Microwave and Millimeter-Wave Technology)

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