The Design of a Monolithic MSTP ASIC(Integrated Electronics)

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概要

• 論文の詳細を見る

• A highly integrated monolithic Multi-Service Transport Platform (MSTP) ASIC MSEOSX8-6 incorporating more than 26M transistors has been fabricated with 0.18μm CMOS technology. The chip is a powerful monolithic MSTP ASIC that supports RPR applications and serves as a generic building block for MSTP network. To accelerate the chip design, we devise a novel methodology called Embedded Reduced Self-Tester (ERST), which integrates the reduced self-tester structure into the chip to shorten the duration of dynamic simulation. Moreover, we divide the design into 12 smaller Hierarchical Layout Blocks (HLB) to enable parallel layout. Resultantly, the whole design has been completed in 5 months, which saves at least 80% of the design cycle in all.

• 社団法人電子情報通信学会の論文
• 2006-08-01

著者

• Zeng Lie-guang

  Department Of Electronic Engineering Tsinghua Univ.

• Zhang Chao

  School Of Aerospace Tsinghua Univ.

• Wang Peng

  State Key Laboratory On Microwave And Digital Communications Tsinghua National Laboratory For Inform

• WANG Peng

  Faculty of Information Engineering, Univ.

• HUA Nan

  Department of Electronic Engineering, Tsinghua Univ.

• JIN De-peng

  Department of Electronic Engineering, Tsinghua Univ.

• Hua Nan

  Department Of Electronic Engineering Tsinghua Univ.

• Jin De-peng

  Department Of Electronic Engineering Tsinghua Univ.

• Wang Peng

  Faculty Of Bioindustry Tokyo University Of Agriculture

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