A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder(VLSI Systems)

スポンサーリンク

概要

• 論文の詳細を見る

• A novel high-speed and area-efficient Reed-Solomon decoder is proposed, which employs pipelining architecture of minimized modified Euclid (ME) algorithm. The logic synthesis and simulation results of its VLSI implementation show that it not only can operate at a higher clock frequency, but also consumes fewer hardware resources.

• 社団法人電子情報通信学会の論文
• 2007-08-01

著者

• Ma Lin-hua

  Engineering College Airforce Engineering University:(present Office)state Key Lab. Of Integrated Ser

• Wang Wei-min

  Engineering College Airforce Engineering University

• BI Du-yan

  Engineering College, Airforce Engineering University

• DU Xing-min

  Engineering College, Airforce Engineering University

• Bi Du-yan

  Engineering College Airforce Engineering University

• Du Xing-min

  Engineering College Airforce Engineering University

関連論文

• A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder(VLSI Systems)

スポンサーリンク