Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits(Simulation and Verification,<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In MTCMOS circuit, voltage on virtual ground fluctuates due to a discharge current of a logic cell. This event affects to the cell delay and makes static timing analysis (STA) difficult. In this paper, we propose a delay modeling and static STA methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. This technique enables to calculate the cell delay considering the delay increase by the voltage fluctuation of virtual ground line. Experimental results show that the proposed methodology enables to estimate the cell delay and the critical path delay within 8% errors compared with SPICE simulation.

• 社団法人電子情報通信学会の論文
• 2006-12-01

著者

• Usami Kimiyoshi

  Graduate School Of Engineering Shibaura Institute Of Technology

• OHKUBO Naoaki

  Graduate School of Engineering, Shibaura Institute of Technology

• Ohkubo Naoaki

  Graduate School Of Engineering Shibaura Institute Of Technology

関連論文

• Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits(Simulation and Verification,VLSI Design and CAD Algorithms)

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