Source/Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices(Device,<Special Section>Low-Power, High-Speed LSIs and Related Technologies)

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概要

• 論文の詳細を見る

• Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gateinduced drain leakage (GIDL). Optimization of FinFET structure including source/drain (S/D) profile was carried out for hp45 low standby power (LSTP) device whose gate length (L_g) is equal to 25nm. GIDL is reduced by using gradual and offset S/D profile while degradation of drive current is minimized. Through the optimization of lateral straggle and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10nm fin width.

• 社団法人電子情報通信学会の論文
• 2007-04-01

著者

• Hane Masami

  System Devices Research Laboratories Nec Corporation

• TANAKA Katsuhiko

  System Devices Research Laboratories, NEC Corporation

• TAKEUCHI Kiyoshi

  System Devices Research Laboratories, NEC Corporation

• Tanaka Katsuhiko

  System Devices Research Laboratories Nec Corporation

• Takeuchi Kiyoshi

  System Devices Research Laboratories Nec Corporation

関連論文

• Source/Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices(Device,Low-Power, High-Speed LSIs and Related Technologies)

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