Lowering the Error Floors of Irregular LDPC Code on Fast Fading Environment with Perfect and Imperfect CSIs(Wireless Communication Technologies)
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概要
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Irregular LDPC codes can achieve better error rate performance than regular LDPC codes. However, irregular LDPC codes have higher error floors than regular LDPC codes. The Ordered Statistic Decoding (OSD) algorithm achieves approximate Maximum Likelihood (ML) decoding. ML decoding is effective to lower error floors. However, the OSD estimates satisfy the parity check equation of the LDPC code even the estimates are wrong. Hybrid decoder combining LLR-BP decoding algorithm and the OSD algorithm cannot also lower error floors, because wrong estimates also satisfy the LDPC parity check equation. We proposed the concatenated code constructed with an inner irregular LDPC code and an outer Cyclic Redundancy Check (CRC). Owing to CRC, we can detect wrong codewords from OSD estimates. Our CRC-LDPC code with hybrid decoder can lower error floors in an AWGN channel. In wireless communications, we cannot neglect the effects of the channel. The OSD algorithm needs the ordering of each bit based on the reliability. The Channel State Information (CSI) is used for deciding reliability of each bit. In this paper, we evaluate the Block Error Rate (BLER) of the CRC-LDPC code with hybrid decoder in a fast fading channel with perfect and imperfect CSIs where 'imperfect CSI' means that the distribution of channel and those statistical average of the fading amplitudes are known at the receiver. By computer simulation, we show that the CRC-LDPC code with hybrid decoder can lower error floors than the conventional LDPC code with hybrid decoder in the fast fading channel with perfect and imperfect CSIs. We also show that combining error detection with the OSD algorithm is effective not only for lowering the error floor but also for reducing computational complexity of the OSD algorithm.
- 2007-03-01
著者
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GOUNAI Satoshi
Graduate School of Electrical Engineering, Tokyo University of Science
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OHTSUKI Tomoaki
Department of Information and Computor Science, Keio University
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Gounai Satoshi
Graduate School Of Electrical Engineering Tokyo University Of Science
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Ohtsuki T
Faculty Of Science And Technology Keio University
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KANEKO Toshinobu
Department of Electrical Engineering, Faculty of Science and Technology
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Kaneko Toshinobu
Department Of Electrical Engineering Faculty Of Science And Technology
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Kaneko Toshinobu
Tokyo Univ. Sci. Noda‐shi Jpn
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Kaneko Toshinobu
Tokyo Univ. Of Sci. Noda‐shi Jpn
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Ohtsuki Tomoaki
Department Of Computer And Information Keio University
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Kaneko Toshinobu
Department Of Electric Engineering Science University Of Tokyo
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