Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation(Devices/Circuits for Communications)

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概要

• 論文の詳細を見る

• This paper proposes the new radix-2^4 FFT algorithm and an efficient pipeline FFT architecture based on the algorithm for wideband OFDM systems. The proposed pipeline architecture has the same number of multipliers as that of the radix-2^2 algorithm. However, the multiplication complexity is reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers. From the synthesis simulations of a standard 0.35μm CMOS SAMSUNG process, the proposed CSD constant complex multiplier achieved a reduction of more than 60% of the power consumption/area when compared with the conventional programmable complex multiplier.

• 社団法人電子情報通信学会の論文
• 2006-04-01

著者

• LIM Myoung-Seob

  Chonbuk National University

• OH Jung-Yeol

  Electronics and Telecommunications Research Institute

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• Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation(Devices/Circuits for Communications)

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