Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding(<Special Section>Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2005))

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概要

• 論文の詳細を見る

• This paper describes the efficiency of VLSI architecture for UMHexagonS (hybrid Unsymmetrical cross Multi Hexagon grid Search) matching algorithm. This algorithm is used for ME (Motion Estimation) of H.264/AVC video compression standard. The UMHexagonS is called a hybrid algorithm since it uses different kinds of searching patterns. VLSI architecture based on UMHexagonS is designed to provide a good tradeoff between gate sizes and high throughput. We implemented this architecture with about 309K gates and 1/1792 throughput [block/cycle] for a search range of 16 and 4×4 macro blocks using synthesizable Verilog HDL.

• 社団法人電子情報通信学会の論文
• 2006-06-01

著者

• Shin Yil-mi

  Dept. Of Electronics Engineering Konkuk Univ.

• Byeon Myung-suk

  Dept. Of Electronics Engineering Konkuk Univ.

• CHO Yong-Beom

  NITRI (Next Generation Innovative Technology Research Institute), Konkuk Univ.

• Cho Yong-beom

  Nitri (next Generation Innovative Technology Research Institute) Konkuk Univ.

関連論文

• Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding(Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2005))

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