A Highly Linearized CMOS Multiplier with a Controlled Tail Current Source(<Special Section>Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2005))

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概要

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• This paper proposes a linearized multiplier using the MOS transistors. The proposed circuit can be realized by adding two voltage shifters and some current mirrors to the conventional circuit. Especially, these additional voltage shifters can be saved when the proposed circuit is used as a transconductor. The proposed circuit is driven by a controlled tail current source. A technique to reduce the effect of the mobility reduction is proposed. First, the output current of the conventional transconductor is analytically derived and its problem is pointed out. Secondly, the proposed circuit is shown. The proposed method is accomplished by taking the mobility reduction into account. The validity of the proposed method is confirmed through both of Spice simulation and experiment. Finally, the proposed circuit is fabricated in the 1.2μm CMOS process. The second-order and the third-order distortions are about-55dB and -64dB, respectively for a 0.5Vp-p sinusoidal input signal.

• 社団法人電子情報通信学会の論文
• 2006-06-01

著者

• Ishibashi Yukio

  Graduate School Of Systems And Information Engineering University Of Tsukuba

• SHOUNO Kazuhiro

  Graduate School of Systems and Information Engineering, University of Tsukuba

• HORI Tasuku

  Master's Program in Science and Engineering, University of Tsukuba

• Hori Tasuku

  Master's Program In Science And Engineering University Of Tsukuba

• Shouno Kazuhiro

  Graduate School Of Systems And Information Engineering University Of Tsukuba

関連論文

• A Highly Linearized CMOS Multiplier with a Controlled Tail Current Source(Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2005))

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