Low-Voltage Analog Switch in Deep Submicron CMOS : Design Technique and Experimental Measurements(Analog Signal Processing)

スポンサーリンク

概要

• 論文の詳細を見る

• This paper concerns the design, implementation and subsequent experimental validation of a low-voltage analog CMOS switch based on a gate-bootstrapped method. The main part of the proposed circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. An important attribute of the design is that the ON-resistance is nearly constant. A test chip has been designed and fabricated using a TSMC 0.18μm CMOS process (single poly, n-well) to confirm the operation of the circuit for a supply voltage of down to 0.65V.

• 社団法人電子情報通信学会の論文
• 2006-04-01

著者

• Roberts Gordon

  Department Of Electrical Engineering Mcgill University

• FAYOMI Christion

  Computer Science Department, Universite du Quebec a Montreal

• SAWAN Mohamad

  Department of Electrical Engineering, Ecole Polytechnique de Montreal

• Sawan Mohamad

  Department Of Electrical Engineering Ecole Polytechnique De Montreal

• Fayomi Christion

  Computer Science Department Universite Du Quebec A Montreal

関連論文

• Low-Voltage Analog Switch in Deep Submicron CMOS : Design Technique and Experimental Measurements(Analog Signal Processing)

スポンサーリンク