The Potential and the Drawbacks of Underlap Single-Gate Ultrathin SOI MOSFET(ELECTRICAL AND ELECTRONIC ENGINEERING,50th anniversary edition)
スポンサーリンク
概要
- 論文の詳細を見る
This paper describes the performance prospect of underlapped single-gate ultra-thin (USU) SOI MOSFET with a low-k or high-k gate dielectric from the viewpoint of both digital and analog applications. Increase in underlap length suppresses the threshold voltage variation as well as suppression of short-channel effects. In addition, the thickness of the SOI layer directly impacts the maximization of drive current (i. e., minimization of intrinsic delay time). Since the fringe capacitance is reduced in introduction of underlap region, effective gate capacitance is also reduced, while voltage gain of the device rises. Since apparent rise of cut-off frequency stems from the reduction of voltage gain, advancement of analog performance is inherently limited. Use of a high-k gate dielectric basically reduces the gate-induced drain leakage (GIDL) current, while short-channel effects are degraded. In the case of very high dielectric constant, however, a very high electric-field region appearing far from the gate edge becomes a new source of high GIDL current. So, optimization of the dielectric constant of the gate insulator is required.
- 関西大学の論文
著者
-
Omura Yasuhisa
Grad. School Of Eng. Kansai University
-
YOSHIOKA Yoshimasa
Grad. School of Eng., Kansai University
-
HAMADA Mitsuo
Grad. School of Eng., Kansai University
-
Hamada Mitsuo
Grad. School Of Eng. Kansai University
-
Yoshioka Yoshimasa
Grad. School Of Eng. Kansai University