CMOS digitally controlled programmable gain amplifier (PGA) with DC offset cancellation(Session8A: Si Devices III)

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概要

• 論文の詳細を見る

• This paper presents a programmable gain amplifier (PGA) to integrate a RF direct-conversion receiver for DVB-H/T-DMB standards. The proposed CMOS PGA includes both a digital controlled gain amplifier to improve linearity and DC input offset voltage cancellation. The PGA for the mobile TVs requires specifications such as 3-dB bandwidth of I MHz and wide dynamic range of more than 40dB. The PGA is composed of three parts, an amplification core, a digital gain control circuit and a DC offset cancellation circuit. The PGA (amplification) core block is a current mode amplifier with a digital gain controller consists of switched resister array structure. The DC offset cancellation block is based on RC low-pass filter which is connected to input of the PGA core to feedback a nearly DC signal, so that nearly DC signal has a high close-loop gain for elimination of the offset voltage. The proposed PGA is designed using TSMC 0.25μm CMOS technology library, and which shows dynamic range of 40dB with 2.5dB gain steps throughout 2MHz desired-3-dB bandwidth. All Circuits were designed with the supply voltage of 3.3V. The power dissipation is 8.36mW.

• 社団法人電子情報通信学会の論文
• 2008-07-02

著者

• Burm Jinwook

  Faculty Of Engineering Sogang University

• Kim Kyunghoon

  Faculty of Engineering, Sogang University

• Kim Kyunghoon

  Faculty Of Engineering Sogang University

関連論文

• CMOS digitally controlled programmable gain amplifier (PGA) with DC offset cancellation(Session8A: Si Devices III)
• CMOS digitally controlled programmable gain amplifier (PGA) with DC offset cancellation(Session8A: Si Devices III)

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