高性能Si-薄膜トランジスタの耐圧に及ぼすソース-ドレイン不純物プロファイルの効果(<小特集>ディスプレイ-IDW'06を中心に-)

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概要

• 論文の詳細を見る

• The effects of the source and drain junction depth on breakdown voltage of high-performance Si TFTs have been studied. It is found that decreasing the junction depth results in a substantial increase in the source-drain breakdown voltage (V_<BD>). The improvement in V_<BD> is primarily due to suppression of parasitic bipolar gain. Reduced parasitic bipolar gain originates from the suppression of the body potential elevation in the shallow junction structure, that allows for penetration of the excess holes beneath the source n+ region.

• 2007-09-01

著者

• Mitani Masahiro

  Altedec

• Tsuboi Shinzo

  Altedec

• Kawachi Genshiro

  ALTEDEC

• Okada Takashi

  ALTEDEC

関連論文

• Effects of Source and Drain Impurity Profile on Breakdown Voltage of High-Performance Si TFTs
• 高性能Si-薄膜トランジスタの耐圧に及ぼすソース-ドレイン不純物プロファイルの効果(ディスプレイ-IDW'06を中心に-)

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