FFT with reduced complexity and its application to a CORDIC-based reconfigurable systolic array (ソフトウェア無線)

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概要

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• This paper presents a new method by which FFT/IFFT can be implemented on a CORDIC-based processor. A radix-2 FFT is considered, where in contrast to conventional method of implementing FFT on purely CORDIC-based processors, the proposed method produces FFT results without performing trivial sign reversal operation. Therefore, any additional overhead that arises from sign reversal in the conventional methods can be avoided. With an eight-point IFFT as an example, it is shown that the proposed method reduces by 12.5% total number of CORDIC resources that are utilized. In addition, the proposed concept was implemented on CORSAEngine, which is a reconfigurable CORDIC-based processor that has recently been developed by NEC Corporation. The implementation that was based on a 576-point IDFT showed that in comparison to conventional approach of implementing CORDIC-based IDFT, the proposed method increases throughput by a factor of 20%.

• 社団法人電子情報通信学会の論文
• 2008-01-17

著者

• Okello James

  System Ip Core Laboratory Nec Corporation

• SEKI Katsutoshi

  System IP Core Research Laboratories, NEC Corporation

• KOBORI Tomoyoshi

  System IP Core Research Laboratories, NEC Corporation

• IKEKAWA Masao

  System IP Core Research Laboratories, NEC Corporation

• Ikekawa Masao

  System Ip Core Laboratory Nec Corporation

• Seki Katsutoshi

  System Ip Core Laboratory Nec Corporation

• Kobori Tomoyoshi

  System Ip Core Laboratory Nec Corporation

関連論文

• FFT with reduced complexity and its application to a CORDIC-based reconfigurable systolic array (ソフトウェア無線)
• Interference mitigation for WCDMA using QR decomposition and a CORDIC-based reconfigurable systolic array (ソフトウェア無線)

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