An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors(Special Issue on the 1994 VLSI Circuits Symposium)

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概要

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• A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 μm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4× the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.

• 1995-06-25

著者

• Lundberg Jim

  Motorola Inc.

• Dunning Jim

  Motorola, Inc.

• Garcia Gerald

  Motorola, Inc.

• Nuckolls Ed

  High-Performance Embedded Systems Division, Motorola, Inc.

• Garcia Gerald

  Motorola Inc.

• Dunning Jim

  Motorola Inc.

• Nuckolls Ed

  High-performance Embedded Systems Division Motorola Inc.

関連論文

• An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors(Special Issue on the 1994 VLSI Circuits Symposium)

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