A Wide-Bandwidth Low-Voltage PLL for PowerPC^<TM> Microprocessors(Special Issue on the 1994 VLSI Circuits Symposium)

スポンサーリンク

概要

• 論文の詳細を見る

• A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 μm CMOS technology is described. The PLL supports internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC^<TM> microprocessors.^1 The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 μs, PLL power dissipation below 10mW as well as phase error and jitter below ±100 ps have been measured. The total area of the PLL is 0.52mm^2.

• 1995-06-25

著者

• Alvarez Jose

  Risc Division Motorola

• Sanchez Hector

  Somerset Design Center, Motorola

• Gerosa Gianfranco

  Semiconductor sector, Motorola

• Countryman Roger

  Microprocessor and Memory Products Group, Motorola

• Sanchez Hector

  Somerset Design Center Motorola

• Countryman Roger

  Microprocessor And Memory Products Group Motorola

• Gerosa Gianfranco

  Semiconductor Sector Motorola

関連論文

• A Wide-Bandwidth Low-Voltage PLL for PowerPC^ Microprocessors(Special Issue on the 1994 VLSI Circuits Symposium)

スポンサーリンク