3-dimensional vertically integrated nano-shell all-around-gate MOSFET (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))

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概要

• 論文の詳細を見る

• This paper reports a novel 3-dimensional vertical nano-shell all-around-gate MOSFET for ultimate device scaling. The vertical nano-shell structure can be realized by introduction of a silicon thin-body formed by chemical vapor deposition (CVD) of poly-silicon and subsequent solid phase crystallization (SPC) as well as incorporation of an electrically independent inner-gate. It was verified that the vertical nano-shell MOSFET offers immunity to short-channel effects through a comparison of device performances between a nano-shell structure (double all-around-gate) and a nano-wire structure (single all-around-gate) with the aid of a SILVACO[○!R] 3-D simulator. With diverse modulations of the bias from the independently operated inner gate, the electrical characteristics of the MOSFET and the feasibility of application to a low-power transistor are investigated.

• 社団法人電子情報通信学会の論文
• 2007-06-18

著者

• Choi Yang-kyu

  School Of Electrical Engineering & Computer Science Korea Advanced Institute Of Science And Tech

• Kim Chung-Jin

  School of Electrical Engineering & Computer Science, Korea Advanced Institute of Science and Technol

• Kim Chung-jin

  School Of Electrical Engineering & Computer Science Korea Advanced Institute Of Science And Tech

関連論文

• 3-dimensional vertically integrated nano-shell all-around-gate MOSFET (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• 3-dimensional vertically integrated nano-shell all-around-gate MOSFET (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))

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