A-3-6 Floorplan Design with Boundary Constraints

スポンサーリンク

概要

• 論文の詳細を見る

• The design of floorplan is the most important step in the VLSI design. In a floorplan, some modules as I/O (Input/Output) should be placed on the boundary of chips, which is called the boundary constraint problem. In this paper, we propose an algorithm for solving the boundary constraint problem by the (Q-sequences and we seek the optimum solution by G.A (Genetic Algorithms).

• 社団法人電子情報通信学会の論文
• 2005-09-07

著者

• Zhao Hua-an

  Kyushu Kyoritsu University

• LIU Chen

  Nanjing University of Posts and Telecommunications

• Yang Zhenyu

  Kyushu Kyoritsu University

• WANG Weigang

  Nanjing University of Posts and Telecommunications

• MIHARA Tetsuji

  Kyushu Kyoritsu University

• Liu Chen

  Nanjing Univ. Posts And Telecommunications Nanjing Chn

関連論文

• EQ-Sequences for Coding Floorplans(Floorplan)(VLSI Design and CAD Algorithms)
• A-3-6 Floorplan Design with Boundary Constraints
• Diagonal Block Orthogonal Algebraic Space-Time Block Codes(Communications and Wireless Systems, Recent Advances in Circuits and Systems-Part 1)

スポンサーリンク