Accelerating Verification with Reusable Testbench(Dependable Computing)

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概要

• 論文の詳細を見る

• The increased complexity in system design has brought an explosive growth in functional verification time. Thus, many verification methodologies have been proposed to reduce it. One of them is the co-emulation method in which the hardware accelerator and software simulator work together. This paper presents an effective testbench architecture for accelerated verification and reuse of parts of the testbench in co-emulation. The testbench is divided into a synthesizable part which can be hardware accelerated and a non-synthesizable part which remains on the software simulator. The split blocks of the testbench can be reused in other test environments. Experiments with real world systems show that the proposed verification environment has over 31% higher performance than that of the conventional co-emulation environment.

• 社団法人電子情報通信学会の論文
• 2006-02-01

著者

• Park Sin-chong

  The System Integration Technology Institute Information And Communications University

• Choi Hae-wook

  The System Integration Technology Institute Information And Communications University

• Son Jungbo

  The System Integration Technology Institute Information And Communications University:with The Elect

関連論文

• Accelerating Verification with Reusable Testbench(Dependable Computing)

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