Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-μm CMOS Technology (Microwaves, Millimeter-Waves)

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概要

• 論文の詳細を見る

• A low-noise, low-power 10-GHz CMOS VCO was developed using cost-effective 0.18-μm CMOS technology. A complementary cross-coupled topology was employed to decrease the power dissipation and phase noise. The fabricated VCO demonstrates a low phase noise of -106 dBc/Hz at an offset frequency of 1MHz and a low power dissipation of 4.4mW.

• 社団法人電子情報通信学会の論文
• 2006-02-01

著者

• Ohhata Kenichi

  The Dept. Of Electrical And Electronic Engineering Kagoshima Univ.

• HARASAWA Katsuyoshi

  the LSI Module Dept. II, Hitachi Hybrid Network Co., Ltd.,

• HONDA Makoto

  the LSI Module Dept. II, Hitachi Hybrid Network Co., Ltd.,

• YAMASHITA Kiichi

  the Dept. of Electrical and Electronic Engineering, Kagoshima Univ.

• Yamashita Kiichi

  The Dept. Of Electrical And Electronic Engineering Kagoshima Univ.

• Harasawa Katsuyoshi

  The Lsi Module Dept. Ii Hitachi Hybrid Network Co. Ltd.

• Honda Makoto

  The Lsi Module Dept. Ii Hitachi Hybrid Network Co. Ltd.

• Ohhata Kenichi

  The Department Of Electrical And Elecironics Engineering Kagoshima University

関連論文

• Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-μm CMOS Technology (Microwaves, Millimeter-Waves)
• Low-Offset, Low-Power Latched Comparator Using Capacitive Averaging Technique

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