Channel-Count-Independent BIST for Multi-Channel SerDes (Interface and Interconnect Techniques, <Special Section> VLSI Design Technology in the Sub-100nm Era)

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概要

• 論文の詳細を見る

• This paper describes a BIST circuit for testing SoC integrated multi-channel serializer/deserializer (SerDes) macros. A newly developed packet-based PRBS generator enables the BIST to perform atspeed testing of asynchronous data transfers. In addition, a new technique for chained alignment checks between adjacent channels helps achieve a channel-count-independent architecture for verification of multi-channel alignment between SerDes macros. Fabricated in a 0.13-μm CMOS process and operating at > 500MHz, the BIST has successfully verified all SerDes functions in at-speed testing of 5-Gbps×20-ch SerDes macros.

• 社団法人電子情報通信学会の論文

著者

• Fukaishi Muneo

  System Devices Research Labs Nec Corporation

• YAMAGUCHI Kouichi

  System Devices Research Labs, NEC Corporation

• Yamaguchi Kouichi

  System Devices Research Labs Nec Corporation

関連論文

• Channel-Count-Independent BIST for Multi-Channel SerDes (Interface and Interconnect Techniques, VLSI Design Technology in the Sub-100nm Era)

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