An Enhanced BSA for Floorplanning (VLSI Design Technology and CAD)

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概要

• 論文の詳細を見る

• In the floorplan design of System-on-Chip (SOC), Buffer Site Approach (BSA) has been used to relax the buffer congestion problem. However, for a floorplan with dominant wide bus, BSA may instead worsen the congestion. Our proposed Enhanced Buffer Site Approach (EBSA) extends existing BSA in a way that buffers of dominant wide bus can be distributed more evenly while reserving the same fast operation speed as BSA does. Experiments have been performed to integrate our model into an iterative floorplanning algorithm, and the results reveal that buffer congestion in a floorplan with dominant wide bus can be much abated.

• 社団法人電子情報通信学会の論文
• 2006-02-01

著者

• Tong Yang-shan

  Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National Taiw

• Chen Sao

  Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National Taiw

• FANG Jyh

  Department of Electrical Engineering, National Taipei University of Technology

• Fang Jyh

  Department Of Electrical Engineering National Taipei University Of Technology

関連論文

• An Enhanced BSA for Floorplanning (VLSI Design Technology and CAD)

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