A new DRAM Cell for SoC (System on a Chip) Devices : Planar DRAM Cell, Based On Logic Process

概要

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A new DRAM Cell for SoC (System on a Chip) Devices is introduced and discussed. An improvement in electrical characteristics of DRAM Cell is obtained by PMOS type cell instead of NMOS. It is of DRAM Cell's leakage currents. The leakage currents are related to data retention time. The PMOS DRAM Cell also results in lower capacitance and lower tr. performance. However, the good data retention time may outweigh the disadvantages and can significantly improve DRAM characteristics in SoC Product. For the substrate (N-Well) bias condition of PMOS DRAM Cell higher than operating voltage (Vcc), it is good immunity for noises and voltage's bouncing on a chip level. This detailed study shows that the PMOS DRAM Cell has several unique advantages over the NMOS DRAM Scheme such as a small cell tr. leakage current and cell capacitor's leakage. Also, it is suitable for high-performance logic devices included in DRAM's.
社団法人電子情報通信学会の論文
2002-06-24