A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting(VLSI Circuit, <Special Section>VLSI Design and CAD Algorithms)

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概要

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• This paper presents a standard cell-based frequency synthesizer with dynamic frequency counting (DFC) for multiplying input reference frequency by N times. The dynamic frequency counting loop uses variable time period to estimate and tune the frequency of digitally-controlled oscillator (DCO) which enhances frequency detection's resolution and loop stability. Two ripple counters serve as frequency estimator. Conventional phase-frequency detector (PFD) thus is replaced with a digital arithmetic comparator to yield a divider-free circuit structure. Additionally, a 15 bits DCO with the least significant bit (LSB) resolution 1.55ps is designed by using the gate capacitance difference of 2-input NOR gate in fine-tuning stage. A modified incremental data weighted averaging (IDWA) circuit is also designed to achieve improved linearity of DCO by dynamic element matching (DEM) skill. Based on the proposed standard cell-based frequency synthesizer, a test chip is designed and verified on 0.35-μm complementary metal oxide silicon (CMOS) process, and has a frequency range of (18-214)MHz at 3.3V with peak-to-peak (P_k-P_k) jitter of less than 70ps at 192MHz/3.3V.

• 2005-12-01

著者

• Lee Chen

  Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University

• Chen Pao

  Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University:de

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• A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting(VLSI Circuit, VLSI Design and CAD Algorithms)
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