On the Computational Synthesis of CMOS Voltage Followers(Circuit Synthesis, <Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• A systematic method is introduced to the computational synthesis of CMOS voltage followers (VFs). The method is divided in three steps : generation of the small-signal circuitry by selection of nullators to model the behavior of a VF, and addition of norators to form nullatornorator joined-pairs; generation of the bias circuitry by addition of ideal biases according to the properties of nullators and norators; and synthesis of the joined-pairs by MOSFETs, and of the current-biases by CMOS current mirrors. It is shown that the proposed synthesis method has the capability to generate already known and new CMOS VF topologies.

• 社団法人電子情報通信学会の論文
• 2005-12-01

著者

• Tlelo Cuautle

  Electronics Department With The Integrated-circuit Design Group At Inaoe-mexico

• Torres Munoz

  Conacyt-mexico Inaoe

• TORRES PAPAQUI

  CONACyT-MEXICO, INAOE

• Torres Papaqui

  Conacyt-mexico Inaoe

関連論文

• On the Computational Synthesis of CMOS Voltage Followers(Circuit Synthesis, VLSI Design and CAD Algorithms)

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