Recent Developments in Electrical Linewidth and Overlay Metrology for Integrated Circuit Fabrication Processes

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Electrical linewidth measurements have been extracted from test structures replicated in planar films of monocrystalline silicon that were electrically insulated from the bulk-silicon substrate by a layer of silicon dioxide formed by separation by the implantation of oxygen (SIMOX) processing. Appropriate selection of the surface orientation of the starting material, the design and orientation of the structure's features, and patterning by a lattice-plane selective etch provide features with planar, atomically smooth sidewalls and rectangular cross sections. The primary motivation for this approach is to attempt to overcome the serious challenge posed by methods divergence to the certification of linewidth reference-materials for critical-dimension (CD) instrument calibration and related tasks. To enhance the physical robustness of reference features with deep submicrometer linewidths, the new test structure embodies short reference-segment lengths and arbitrarily wide voltage taps. Facilities for reconciliation of measurements extracted from the same feature by all normally practiced techniques are also implemented. In overlay metrology, electrical inspection of two types of hybrid overlay targets allows pixel calibration of, and shift extraction from, the overlay instruments. The overall strategic focus of this research is to resolve methods-divergence issues and possibly to develop universal deep-submicrometer linewidth reference materials for CD instruments and techniques for instrument- and process-specific shift extraction for optical overlay metrology.
社団法人応用物理学会の論文
1996-12-30

Recent Developments in Electrical Linewidth and Overlay Metrology for Integrated Circuit Fabrication Processes

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