10 GHz Low-Noise Low-Power Monolithic Integrated VCOs in Digital CMOS Technology(Electronic Circuits)

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概要

• 論文の詳細を見る

• This paper presents the design of low-power low-noise 10 GHz CMOS monolithic integrated LC VCOs suitable for data clock recovery architectures in optical receivers of SDH (STM-64) and SONET (OC-192). Optimizations of device parameters and passive components are given in detail. For passive components, differential and single-ended inductor structures as well as MOS varactors with and without lightly doped drain/source (LDD) implantation have been investigated. The VCOs implemented in a 0.18μm process demonstrate the single-side-band phase noise of as low as -107 dBc/Hz at 1 MHz offset and 21% tuning range while consuming only 7 mW under 1.8 V supply.

• 社団法人電子情報通信学会の論文
• 2006-01-01

著者

• Thiede Andreas

  Department Of Ee & It University Of Paderborn

• Gu Zheng

  Infineon Technologies Ag

関連論文

• 10 GHz Low-Noise Low-Power Monolithic Integrated VCOs in Digital CMOS Technology(Electronic Circuits)

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