A Hardware Cost Estimation Method For Design Reuse

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概要

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• In this paper, we describe a hardware cost estimation methodology for designs with hard IPs, soft IPs, and gate-level netlists. It is based on a hierarchical floorplanning method which uses a hierarchical partitioning and placement improvement by using the region refinement algorithm. If the given circuit has large soft IPs, we partition them for efficient and flexible floorplanning. At each level of the hierarchy, routing area estimation is performed. Experimental results show that our estimation method is promising.

• 1999-07-22

著者

• Shin Hyunchul

  School Of Electrical And Computer Engineering Hanyang University

• Kim Wonjong

  School of Electrical Engineering & Computer Science, Hanyang University

関連論文

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