Low Power, High Performance Megacell Circuit Technique for Sub-1V CMOS VLSI

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概要

• 論文の詳細を見る

• Low power circuit techniques have been developed to realize the highest possible performance for the megacells including embedded 128kb SRAM and 32-b ALU, which are designed to operate at 160MHz clock frequency under 1V power supply.In order to achieve the best trade-off between power consumption and gate delay in the low power CMOSICs, the half micrometer low power CMOS technology is also proposed.The unbalance between PMOS and NMOS threshold voltages facilitates the high performance circuit design at the minimal standby current.As the sub-1V CMOS circuit performance becomes very sensitive to the temperature and process variation of threshold voltages in particular, the threshold voltage control circuit is also designed to stabilize the threshold voltages at the intended levels.

• 社団法人電子情報通信学会の論文
• 1998-07-23

著者

• Chung Kyung-ah

  Dept. Of Electronics Engineering Dankook University

• Son Ilhum

  Dept.of Electronics Engineering, Dankook University

• Myoung Daejin

  Dept.of Electronics Engineering, Dankook University

• Lim Jeongsik

  Dept.of Electronics Engineering, Dankook University

• Cho Hoonsik

  Dept.of Electronics Engineering, Dankook University

• Son Ilhun

  Dept. of Electronics Engineering, Dankook University

• Cho Hoonsik

  Dept. Of Electronics Engineering Dankook University

• Lim Jeongsik

  Dept. Of Electronics Engineering Dankook University

• Myoung Daejin

  Dept. Of Electronics Engineering Dankook University

• Son Ilhun

  Dept. Of Electronics Engineering Dankook University

関連論文

• Low Power, High Performance Megacell Circuit Technique for Sub-1V CMOS VLSI
• Low power, High Performance Megacell Circuit Technique for Sub-1V CMOS VLSI

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