High Speed Circuit Design with Matched Delay Technique

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概要

• 論文の詳細を見る

• The matched delay technique is a timing methodology for clock and data delay coordination that produces very high performance integrated circuits. In this methodology, control of path propagation delays combined with careful management of clock skew and data events, is used to design very high speed circuits. In this paper, a CMOS data recovery circuit design based on the matched delay technique is presented.

• 社団法人電子情報通信学会の論文
• 1997-07-24

著者

• Kang Jin-

  Department Of Electronic Electrical And Computer Engineering Inha University

関連論文

• High Speed Circuit Design with Matched Delay Technique
• High Speed Circuit Design with Matched Delay Technique

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