200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits Ternary CAM with New Charge Injection Match Detect Circuits and Bank Selection Scheme

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概要

• 論文の詳細を見る

• The 9.4Mbits Ternary CAM device has been designed and fabricated. The performance of 200MHz/200MSPS(million searches per second) with 3.2W at 1.5V Vdd was achieved. Two new approaches were taken to achieve this performance. One is the Charge Injection Match Detect Circuits (CIMDC) for a very small swing voltage level (about 300mV) of a match line and stable detection of it. The other is the improved Bank Selection Scheme (BSS) with the data-storing method in order to activate only the target bank where a match data is expected to be stored. The 200MSPS is 1.6 times faster and the 3.2W is almost 1/4 less power consumption compared with the conventional design.

• 社団法人電子情報通信学会の論文
• 2003-12-12

著者

• Yoneda Masato

  Sony Corporation

• Furumi Koji

  Sony Corporation

• Takarabe Yukihiro

  Sony Corporation

• Kasai Gen

  SONY Corporation

• 笠井 弦

  SONY Corporation

• 財部 幸広

  SONY Corporation

• 古見 孝治

  SONY Corporation

関連論文

• 200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits Ternary CAM with New Charge Injection Match Detect Circuits and Bank Selection Scheme

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