Breakdown Voltage Improvement of SOI MOSFET Using Gate-Recessed (GR) Structure

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概要

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• A gate-recessed structure is introduced to SOI MOSFET's in order to increase the source-to-drain breakdown voltage. Experimental results show a significant increase in the breakdown voltage compared with that of a conventional SOI MOSFET. From the substrate current measurements and 2D device simulations, we have shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain. We also have shown that the decrease of GIDL current due to the grading of the gate oxide at the drain region results in the significant increase of breakdown voltage at the negative gate biases.

• 社団法人電子情報通信学会の論文
• 1995-07-28

著者

• Park Y.-j.

  Electronics Engineering And Inter-university Semiconductor Research Center

• Choi J.-H.

  Electronics Engineering and Inter-university Semiconductor Research Center

• Min H.-S.

  Electronics Engineering and Inter-university Semiconductor Research Center

関連論文

• Breakdown Voltage Improvement of SOI MOSFET Using Gate-Recessed (GR) Structure

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