Efficient Multiport Static RAM Design

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概要

• 論文の詳細を見る

• In the high performance microprocessors, caches are integrated into a chip with a processor because caches can boost the performance by reducing the latency and increasing the bandwidth for the data transfer to and from processors. Moreover, on-chip multiprocessor which has multiple processors in a chip was recently announced. This paper discusses the design issues of the concurrently accessible caches, and an efficient multiport SRAM design to get an optimization on the SRAM array.

• 社団法人電子情報通信学会の論文
• 1995-07-27

著者

• Kang Jun-woo

  Processor Research Section Electronics And Telecommunications Research Institute

関連論文

• Efficient Multiport Static RAM Design

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