W/TiN Stacked Gate for ULSI Devices

概要

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We introduce the characteristics of cMOSFETs with sputter-deposited W/TiN stacked gate. Very low sheet resistance of 〜3Ω/□ can be obtained with the total gate height of 1500Å. C-V measurement shows that the work function of TiN is slightly shifted toward the valence band from the midgap of silicon, thus the short channel effect of pMOS transistor is considerably suppressed. The gate oxide reliability is improved as the deposition temperature of TiN is increased and becomes comparable to that of poly gate when deposited at 600℃. The results of various physicsal analyses indicate that the initial stoichiometry is most important with respect to the thermal stability of the interface between TiN and SiO_2. As the substrate temperature is increased, the amount of interstitial nitrogen gradually decreases and the resultant diffusion of nitrogen and titanium atoms is also suppressed.
社団法人電子情報通信学会の論文
1995-07-27