A VLSI Architecture Design for Both the QAM and VSB Digital CATV Transceiver

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概要

• 論文の詳細を見る

• In this paper, a transceiver VLSI architecture is proposed for the high speed digital CATV modems, which can perform both the QAM and the VSB transmissions. In this architecture, both the transmitter and receiver employ two or three stages of frequency conversions. The proposed architecture of all-digital QAM/VSB receiver consists of the digital AGC, digital demodulator, T/2 fraction-ally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture for both QAM and VSB digital CATV transceiver can have SNR about 33dB for 64-QAM mode, and about 30dB for 8-VSB mode when the ADC input signal SNR is 43dB and there are ±6kHz of carrier frequency offset, ±200ppm of symbol rate offset, and -82dBc carrier phase-jitter @ 10kHz away from the carrier frequency.

• 社団法人電子情報通信学会の論文
• 1998-01-21

著者

• Shiue Muh-tian

  Department Of Electrical Engineering National Central University

• Huang K‐h

  National Central Univ. Chung‐li Twn

• Huang Kuang-hu

  Department Of Electrical Engineering National Central University

• Way Winston

  Department Of Communication Engineering National Chiao Tung University

• Wang Chorng-Kuang

  Department of Electrical Engineering National Central University

関連論文

• A VLSI Architecture Design for Both the QAM and VSB Digital CATV Transceiver
• A 2.4GHz CMOS Low-IF Receiver

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