A Gate Sizing Approach with Accurate Delay Model for Power and Area Optimization under Delay Constraints

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概要

• 論文の詳細を見る

• In performance driven VLSI design, gate sizing is a very important design process. This paper introduces a new gate sizing approach based on the iterative improvement of linear programming results. A speedup technique for the approach is also proposed in the paper.

• 社団法人電子情報通信学会の論文
• 1995-03-27

著者

• 陳 光球

  Department Of Electronic Engineering Kyoto University

• 小野寺 秀俊

  Department of Electronic EnginEering, Kyoto University

• 田丸 啓吉

  Department of Electronic EnginEering, Kyoto University

• 小野寺 秀俊

  Department of Communications and Computer Engineering, Kyoto University

関連論文

• A Gate Sizing Approach with Accurate Delay Model for Power and Area Optimization under Delay Constraints

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