Multigrain Parallel Processing on Compiler Cooperative OSCAR Chip Multiprocessor Architecture
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概要
- 論文の詳細を見る
This paper describes multigrain parallel processing on OSCAR (Optimally Scheduled Advanced multiprocessoR) chip multiprocessor architecture. OSCAR compiler cooperative chip multiprocessor architecture aims at development of scalable, high effective performance and cost effective chip multiprocessor with ease of use by compiler supports. OSCAR chip multiprocessor architecture integrates simple single issue processors having distributed shared data memory for optimal use of data locality over different loops and fine grain data transfer and synchronization, local data memory for private data recognized by compiler, and compiler controllable data transfer unit for overlapping data transfer to hide data transfer overhead. This OSCAR chip multiprocessor and OSCAR multigrain parallelizing compiler have been developed simultaneously. Performance of multigrain parallel processing on OSCAR chip multiprocessor architecture is evaluated using SPEC fp 2000/95 benchmark suite. When microSPARC like single issue core is used, OSCAR chip multiprocessor architecture gives us 2.36 times speedup in fpppp, 2.64 times in su2cor, 2.88 times in turb3d, 2.98 times in hydro2d, 3-84 times in tomcatv, 3.84 times in mgrid and 3.97 times in swim respectively for four processors against single processor.
- 社団法人電子情報通信学会の論文
- 2003-04-01
著者
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Kimura Keiji
The Authors Are With The Advanced Research Institute For Science And Engineering Waseda University
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KODAKA Takeshi
The authors are with the Department of Electrical Electronics and Computer Engineering, Waseda Unive
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KASAHARA Hironori
The authors are with Advanced Parallelizing Compiler Project
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Kodaka Takeshi
The Authors Are With The Department Of Electrical Electronics And Computer Engineering Waseda Univer
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KASAHARA Hironori
the Department of Electrical Electoronics and Computer Engineering, Waseda University