Remarkable Cycles Reduction in GSM Voice Coding by Reconfigurable Coprocessor with Standard Interface

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概要

• 論文の詳細を見る

• A reconfigurable coprocessor for ETSI-GSM voice coding application domain is presented, synthesized and tested. An average overall reduction of more than 55% cycles with respect to standard RISC processors with DSP features is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption, while standard interfacing technique ensures maximum flexibility.

• 社団法人電子情報通信学会の論文
• 2003-04-01

著者

• Raffo Luigi

  The Authors Are With The Department Of Electrical And Electronic Engineering University Of Cagliari

• GARTA Salvatore

  The authors are with the Department of Electrical and Electronic Engineering, University of Cagliari

• Garta Salvatore

  The Authors Are With The Department Of Electrical And Electronic Engineering University Of Cagliari

関連論文

• Remarkable Cycles Reduction in GSM Voice Coding by Reconfigurable Coprocessor with Standard Interface

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