An Adaptive Reed-Solomon Decoder Using Separate Clocks in the Pipelined Steps(Devices/Circuits for Communications)

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概要

• 論文の詳細を見る

• In this paper, an efficient architecture for an adaptive Reed-Solomon decoder is presented, where the block length n and the message length k can be varied from their minimum allowable values up to their selected values. This eliminates the need of inserting zeros before decoding shortened RS codes. And the error-correcting capability t can be changed adaptively to channel state at every codeword block. The decoder allows efficient decoding in both burst mode and continuous mode, and it permits 3-step pipelined processing based on the modified Euclid's algorithm. Each step in decoding is designed to be clocked by a separate clock. Thus, each step can be efficiently pipelined with no help of multiplexing. Also, it makes it possible to employ no additional buffer even when the decoder input and output clocks are different. The adaptive RS decoder over GF(2^8) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip. It can be used in a wide range of applications because of its versatility.

• 社団法人電子情報通信学会の論文
• 2005-02-01

著者

• Song Moon

  Wonkwang University

• Kong Min

  Wonkwang University

関連論文

• An Adaptive Reed-Solomon Decoder Using Separate Clocks in the Pipelined Steps(Devices/Circuits for Communications)
• Performance Comparison of Stepwise Serial and Parallel Cell Search in WCDMA(Terrestrial Radio Communications)

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