Implementation of a Multi-Class Fair Queueing via Identification of the QoS-Aware Parameters(Switching)

概要

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This paper proposes a novel method of identifying the design parameters for a practical implementation of the fair queueing discipline, which is capable of class-level delay control. The notion of class weight is introduced at first, and then the session weights are determined. This two-phase approach is favorable in terms of the scalability;that is, the overall complexity is dependent upon the number of classes only. We propose a packet scheduler referred to as the DPS (Delay-centric Processor Sharing) scheme which employs those design parameters to deliver classwise delay bound services. The associated admission policy for delay guarantee is also derived. System analysis and derivation of the parameters have their origins in the understanding of the so-called system equation, which describes the dynamics of the class-level service share. The proposed design parameters are QoS-aware in that they are consistently refined depending on the system status. Several numerical and simulation results show that the DPS scheme is advantageous over other ones in terms of both resource efficiency and the robustness. Concerning the scalability, we show that an alternative tagging process of the DPS scheme is implementable with O(1) complexity with no significant degradation in delay performance.
社団法人電子情報通信学会の論文
2004-06-01