A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector(Communication Devices/Circuits)

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概要

• 論文の詳細を見る

• A new clock and data recovery circuit (CDR) is realized for the application of data communication systems requiring GHz-range clock signals. The high frequency jitter is one of major performance-limiting factors in CDR, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Furthermore, optical characteristics for fast locking are achieved with the adaptive delay cell in the phase detector. The circuit is designed based on CMOS 0.25μm fabrication process and its performance is verified by measurement results.

• 社団法人電子情報通信学会の論文
• 2003-07-01

著者

• Lee Jae-wook

  Dept. Of Electrical And Electronic Eng. Yonsei University

• Choi Woo-young

  Dept. Of Electrical And Electronic Eng. Yonsei University

• LEE Cheon-O

  Dept. of Electrical and Electronic Eng., Yonsei University

• Lee Cheon-o

  Dept. Of Electrical And Electronic Eng. Yonsei University

関連論文

• A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector(Communication Devices/Circuits)

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