A Pipeline Structure for High-Speed Step-by-Step RS Decoding

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概要

• 論文の詳細を見る

• Based on a modified step-by-step decoding procedure, a high-speed pipelined Reed-Solomon decoder is presented. The decoder requires only the delay time of three 2-input XOR gates for decoding each coded symbol. The decoder can be operated in a bit rate of Gbits/sec order and thus suitable for the very high speed data transmission systems.

• 社団法人電子情報通信学会の論文
• 2003-02-01

著者

• Wei Che-ho

  Institute Of Electronics National Chiao Tung University

• Chen Tung-chou

  Institute Of Electronics National Chiao Tung University

• WEI Shyuc-Win

  Department of Electrical Engineering,National Chi-Nan University

• Wei Shyuc-win

  Department Of Electrical Engineering National Chi-nan University

関連論文

• A Pipeline Structure for High-Speed Step-by-Step RS Decoding

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