A Hierarchical Cost Estimation Technique for High Level Synthesis

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概要

• 論文の詳細を見る

• The aim of this paper is to present a new cost estimation technique to synthesis hardware from high level circuit description. The scheduling and allocation processes are performed in alternative manner, while using realistic cost measurements models that account for Functional Unit (FU), registers, and multiplexers. This is an improvement over previous works, were most of them use very simple cost models that primarily focus on FU resources alone. These latest, however, are not accurate enough to allow effective design space exploration since the effects of storage and interconnect resources can indeed dominates the cost function. We tested our technique on several high-level synthesis benchmarks. The results indicate that the tool can generate near-optimal bus-based and multiplexor-based architectural models with lower number of registers and buses, while presenting high throughput.

• 社団法人電子情報通信学会の論文
• 2003-02-01

著者

• Motomura Masato

  System Ulsi Research Laboratory Microelectronics Research Laboratories Nec Corporation

• Motomura Masato

  System Ulsi Research Laboratory Silicon Systems Research Laboratories Nec Corporation

• MERIBOUT Mahmoud

  Information Engineering Department,College of Engineering,Sultan Qaboos,University

• Meribout Mahmoud

  Information Engineering Department College Of Engineering Sultan Qaboos University

関連論文

• Cache-Processor Coupling : A Fast and Wide On-Chip Data Cache Design(Special Issue on the 1994 VLSI Circuits Symposium)
• A Hierarchical Cost Estimation Technique for High Level Synthesis

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